Hardware RX/TX timestamp pairs: 64/64
p50 136,837 ns · p99 163,625 ns. Owner-reported server-side NIC timing interval; restoration PASS. Not sub-microsecond, not a full two-host end-to-end latency result.
Request original provenance ↗EVIDENCE / SCOPE-QUALIFIED DISCLOSURE
Public-facing claims are useful only when the measured boundary, source revision and provenance are visible. This register separates demonstrators, bounded software evidence and physical qualification.
EVIDENCE RELEASES / OWNER-APPROVED REGISTER
Published findings update from a read-only release register, independently of the website deployment. Each entry retains its source date, measurement boundary and limitations. Private raw artifacts remain with the researcher.
p50 136,837 ns · p99 163,625 ns. Owner-reported server-side NIC timing interval; restoration PASS. Not sub-microsecond, not a full two-host end-to-end latency result.
Request original provenance ↗Authenticated access, JTAG IDCODE match and SHA-256 precheck reported PASS; no new pin-to-pin timing result established by this check.
13/13 pages and 149/149 resources checked in R10; static R10 documentation remains available for exact historical provenance.
R10 public dossier ↗Last publicly reviewed: 09 November 2026. The register updates after a source-bound result is reviewed and explicitly released; an unreviewed test is never auto-published.
PUBLIC RELEASE / R10 · 09 NOVEMBER 2026
Source-backed public dossier for the thirteen demonstrations. This records the observed campaign; it is neither hardware certification nor proof that the thirteen private source assets have identical native performance.
Zero disagreements in an independent optimised C++20 reference comparison campaign. A separate sanitised subset contains 521,560 comparisons. These are not native performance claims for the private production engines.
Packets observed through generic XDP on Linux virtual ethernet interfaces. This does not demonstrate 10G NIC hardware offload, paired physical timestamping or wire-to-wire latency.
Three TCP/SQLite processes on one host. These cases do not establish inter-host atomic consensus, production recovery or external settlement guarantees.
Observed passive ZAP findings. The High finding concerned a 16-digit sequence inside a publicly exposed SHA-256, assessed as a plausible false positive, not erased. Medium findings included public-resource CORS wildcard observations. This is not a clean penetration-test certificate.
Release record: R10 · 09.11.2026. ZAP original SHA-256: 406abab58b85b464279f0aa5e4119586df3da1c9a7f2dbe933776aa8bd56ff5d. Physical qualification remains independently scoped; no newer unverified FPGA or OVH measurements are represented as completed by this public dossier.
| Evidence layer | Public reading | Required qualification boundary |
|---|---|---|
| 13 public demonstrationsCurrent public pages / R10 communication baseline | Interactive models, problem scope, method and published limitations; links available from the module atlas. | Not evidence of production customer value or automatically applicable to all 48 assets. |
| Source-bound functional evidenceFrontier / Sovereign private reconciliation | Version-specific test results may be discussed in a buyer-safe evidence brief. | A PASS attached to one candidate is not transferable to another revision, a reconstructed original or an adjacent asset. |
| Formal & bounded verificationMethod-specific | Specific properties, step bounds and oracles can be identified during technical diligence. | Formal proof is not implied by test-count coverage, and a model result is not blanket correctness. |
| OVH NIC / PHC / XDPSoftware decisions versus external timestamps | Existing public and internal observations retain their original narrow measurement boundaries. | Hardware capability detection, in-program latency and paired hardware TX/RX are separate stages. The 09 November R22 owner report records 64/64 paired hardware RX/TX timestamps, separate from an independent two-host end-to-end qualification. See the live release register above. |
| FPGA / RTL / JTAGSimulation, timing and pin oracle | RTL simulation, synthesis, JTAG identity, placement timing and physical capture are reported separately. | Successful simulation or programming alone is not calibrated pin-to-pin evidence. Final result must identify hardware revision, toolchain, capture and run. |
| Commercial transferClient-scoped acceptance | Licensing and funded validation considered against a defined use case and acceptance matrix. | No external laboratory endorsement, reference customer, saving figure or certification claimed without matching records. |
EVIDENCE PROVENANCE
This is the release contract for subsequent hardware and software findings.
Asset, immutable revision and tested artifact.
Host, toolchain, clock and hardware topology.
Measurement boundaries, workload and acceptance rules.
Failures, counts, tails and retained exceptions.
Also required: dated evidence pointer and a disclosure decision. A result without those fields stays out of quantified public claims.